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product specification p art name : oel display module customer part id : wisechip part id : UG-6028GDEBF02 doc no. : sas1-0i013-a customer: approved by from: wisechip semiconductor inc. approved by w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . 8, kebei rd 2, science park, chu-nan, taiwan 350, r.o.c. notes: 1. please contact wisechip semiconductor inc. before assigning your product based on this module specifi cation 2. the information contained herein is presented merely to indicate the characteristics and performance of our products. no responsibility is assumed by wisechip semiconductor inc. for any intellectual propert y claims or other problems that may result from application based on the mod ule described herein. 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw i r r e e v v i i s s e e d d h h i i s s t t o o r r y y part number revision revision content revised on UG-6028GDEBF02 a new march 21, 2013 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw ii c c o o n n t t e e n n t t s s r r e e v v i i s s i i o o n n h h i i s s t t o o r r y y ................................................................................................ ................................i c c o o n n t t e e n n t t s s...........................................................................................................................................ii 1 1 . . b b a a s s i i c c s s p p e e c c i i f f i i c c a a t t i i o o n n s s................................................................................................................ 1~5 1. 1 display specifications ....................................................................................................................1 1.2 mechanical specifications...............................................................................................................1 1.3 active area / memory mapping & pixel construction ........................................................................1 1.4 mechanical drawing.......................................................................................................................2 1.5 pin definition ................................................................................................................................3 1.6 block diagram...............................................................................................................................5 2 2 . . a a b b s s o o l l u u t t e e m m a a x x i i m m u u m m r r a a t t i i n n g g s s ........................................................................................................6 3 3 . . optics & e e l l e e c c t t r r i i c c a a l l c c h h a a r r a a c c t t e e r r i i s s t t i i c c s s ....................................................................................... 7~11 3. 1 optics characteristics ....................................................................................................................7 3.2 dc characteristics .........................................................................................................................7 3.3 ac characteristics .........................................................................................................................8 3.3.1 68xx-series mpu parallel interface timing characteristics .....................................................8 3.3.2 80xx-series mpu parallel interface timing characteristics ................................................... 10 3.3.3 serial interface timing characteristics ................................................................................ 11 3.3.4 rgb interface timing characteristics .................................................................................. 12 4 4 . . f f u u n n c c t t i i o o n n a a l l s s p p e e c c i i f f i i c c a a t t i i o o n n ..................................................................................................... 13~16 4. 1 commands ................................................................................................................................. 13 4.2 power down and power up sequence ........................................................................................... 13 4.2.1 power up sequence........................................................................................................... 13 4.2.2 power down sequence ...................................................................................................... 13 4.3 reset circuit ............................................................................................................................... 13 4.4 actual application example .......................................................................................................... 14 5 5 . . r r e e l l i i a a b b i i l l i i t t y y ................................................................................................ ..................................17 5. 1 contents of reliability tests ......................................................................................................... 17 5.2 failure check standard ................................................................................................................ 17 6 6 . . o o u u t t g g o o i i n n g g q q u u a a l l i i t t y y c c o o n n t t r r o o l l s s p p e e c c i i f f i i c c a a t t i i o o n n s s ............................................................................ 18~21 6. 1 environment required ................................................................................................................. 18 6.2 sampling plan ............................................................................................................................. 18 6.3 criteria & acceptable quality level ............................................................................................... 18 6.3.1 cosmetic check (display off) in non-active area................................................................. 18 6.3.2 cosmetic check (display off) in active area........................................................................ 20 6.3.3 pattern check (display on) in active area........................................................................... 21 7 7 . . p p a a c c k k a a g g e e s s p p e e c c i i f f i i c c a a t t i i o o n n s s..............................................................................................................22 8 8 . . p p r r e e c c a a u u t t i i o o n n s s w w h h e e n n u u s s i i n n g g t t h h e e s s e e o o e e l l d d i i s s p p l l a a y y m m o o d d u u l l e e s s ....................................................... 23~25 8. 1 handling precautions ................................................................................................................... 23 8.2 storage precautions..................................................................................................................... 23 8.3 designing precautions ................................................................................................................. 24 8.4 precautions when disposing of the oel display modules ................................................................ 24 8.5 other precautions........................................................................................................................ 24 w w a a r r r r a a n n t t y y ................................................................................................ ........................................25 n n o o t t i i c c e e ................................................................................................ .............................................25 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 1 1 1 . . b b a a s s i i c c s s p p e e c c i i f f i i c c a a t t i i o o n n s s 1.1 display specifications 1) display mode : passive matrix 2) display color : 262,144 colors (maximum) 3) drive duty : 1/48 duty 1.2 mechanical specifications 1) outline drawing : according to the annexed outline drawing 2) number of pixels : 160 ( rgb) 1 28 3) module size : 39.90 48.50 1.60 (mm) 4) panel size : 39.9 0 34.00 1.60 (mm) including glare polarizer 5) active area : 33.575 26.864 (mm) 6) pixel pitch : 0.07 0.21 (mm) 7) pixel size : 0.045 0.194 (mm) 8) weight : 4.55 (g) 10% 1.3 active area / memory mapping & pixel construction s0 ( column 1 ) g126 ( row 127 ) g0 ( row 1 ) s479 ( column 480 ) g127 ( row 128 ) g1 ( row 2 ) detail "a" scale (10:1) 0.045 0.07 0.185 0.21 0.194 0.21 r g b driver ic memory mapping (full 160x3x128) (0,0) (159,127) p0.07x(160x3)-0.025=33.575(a/a) p0.21x128-0.016=26.864(a/a) 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 2 1.4 mechanical drawing 35.575 (v/a) 39.90.2 (panel size) 39.90.2 (cap size) 38.90.3 (polarizer) 0.50.5 (2.163) 310.3 (polarizer) p0.21x128-0.016=26.864 (a/a) 28.864 (v/a) (2.1) (1.1) 320.2 (cap size) 340.2 (panel size) active area 1.69" 160(rgb) x 128 pixels notes: 1. driver ic: seps525 2. die size: 19660um x 1850um 3. cof number: seps525f00 / ut-0825-f01 4. interface: 8-/9-bit 68xx/80xx parallel, 4-wire spi, 6-bit rgb i/f 5. general tolerance: 0.30 6. the total thickness (1.70 max) is without p olarizer protective film & remove tape . the actual assembled total thickness with above materials should be 1.95 max 1.60.1 0.50.5 8 5 10 p0.50x(35-1)=170.05 (w0.350.03) 180.2 30.680.1 (alignment hole) 32.680.2 10 2.85 5 4 14.50.2 the drawing contained herein is the exclusive property of wisechip. it is not allowed to copy, reproduce and or disclose in any formats without permission of wisechip. drawing number 1 of 1 sheet 1:1 scale a3 size rev. b dfe6028cncf13 date item remark 20091110 a original drawing wisechip semiconductor inc. 0.3 mm unless otherwise specified unit tolerance angle dimension general roughness title date by drawn material soda lime / polyimide customer approval signature 1 UG-6028GDEBF02 folding type oel display module pixel number: 160(rgb) x 128, 262144 colors, cof package panel / e. e.e. dora yang p.m. (48.5) remove tape t=0.15mm max polarizer t=0.2mm (3.61) 2-r0.50.05 glue 0.80 max 30.5 (stiffener) 0.30.03 p0.07x(160x3)-0.025=33.575 (a/a) (3.163) (23.2) (2.2) (33.2) (35.44) (5.5) (1.6) (8.7) (42.7) (1.44) "a" detail "a" scale (10:1) 0.045 0.07 0.185 0.21 0.194 0.21 r g b s0 ( column 1 ) g126 ( row 127 ) g0 ( row 1 ) s479 ( column 480 ) g127 ( row 128 ) g1 ( row 2 ) (reference mechnical design) sean lai ivy lo cherry lin 8 14 15 11 13 12 10 9 symbol 2 5 7 6 4 3 1 pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 n.c. (gnd) vsdh vddh vssh iref osca2 osca1 vddio vsynco vss vdd vssh rs csb rdb resetb wrb d17 d16 d15 d14 d13 d12 d11 d10 d9 vddh vsdh n.c. (gnd) vsync hsync dotclk enable cpu ps n. c. (gnd) vsdh vddh vssh ir ef osc a2 osc a1 vddio vsync o vss vdd vssh vddh vsdh n. c. (gnd) rs csb rdb resetb wrb d17 d16 d15 d14 d13 d12 d11 d10 d9 1 35 vsync hsync dotclk enable cpu ps contact side 20120427 20120427 b remove single-side tape 20120427 20120427 20120427 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 3 1.5 pin definition pin number symbol i/o function p p o o w w e e r r s s u u p p p p l l y y 31 vdd p p p o o w w e e r r s s u u p p p p l l y y f f o o r r o o p p e e r r a a t t i i o o n n t his is a voltage supply pin. it must be connected to external source & always be equal to or higher than v ddio . 8 vddio p p p o o w w e e r r s s u u p p p p l l y y f f o o r r i i / / o o p p i i n n t his pin is a power supply pin of i/o buffer. it should be connected to v dd or external source. all i/o signal should have v ih reference to v ddio . when i/o signal pins (cpu, ps, d17~d9 , control signals) pull high, they should be connected to v ddio . 30 vss p g g r r o o u u n n d d o o f f l l o o g g i i c c c c i i r r c c u u i i t t t his is a ground pin. it also acts as a reference for the logic pins. it must be connected to external ground. 3, 33 vddh p p p o o w w e e r r s s u u p p p p l l y y f f o o r r o o e e l l p p a a n n e e l l t hese are the most positive voltage supply pins of the chip. they must be connected to external source. 2, 34 4, 32 vsdh vssh p g g r r o o u u n n d d o o f f o o e e l l p p a a n n e e l l t hese are the ground pins for analog circuits. they must be connected to external ground. vsdh: segment (data driver) vssh: common (scan driver) d d r r i i v v e e r r 5 iref i/o c c u u r r r r e e n n t t r r e e f f e e r r e e n n c c e e f f o o r r b b r r i i g g h h t t n n e e s s s s a a d d j j u u s s t t m m e e n n t t t his is the current reference pin to generate precharge and driving current . a 68k ? resistor should be connected between this pin and v ss . c c l l o o c c k k 7 6 osca1 osca2 i o f f i i n n e e a a d d j j u u s s t t m m e e n n t t f f o o r r o o s s c c i i l l l l a a t t i i o o n n t he frequency is controlled by external 5.1k? resistor between osca1 and osca 2. the oscillator signal is used for system clock generation. when the external clock mode is selected, osca1 is used external clock input. r r g g b b i i n n t t e e r r f f a a c c e e 9 vsynco o v v e e r r t t i i c c a a l l s s y y n n c c h h r r o o n n i i z z a a t t i i o o n n t t r r i i g g g g e e r r i i n n g g s s i i g g n n a a l l wh ile using mcu interface, it must be floating. 10 vsync i v v e e r r t t i i c c a a l l s s y y n n c c h h r r o o n n i i z z a a t t i i o o n n i i n n p p u u t t wh ile using mcu interface, it must be connected to v dd . 11 hsync i h h o o r r i i z z o o n n t t a a l l s s y y n n c c h h r r o o n n i i z z a a t t i i o o n n i i n n p p u u t t wh ile using mcu interface, it must be connected to v dd . 12 dotclk i d d o o t t c c l l o o c c k k i i n n p p u u t t wh ile using mcu interface, it must be connected to v dd . 13 enable i v v i i d d e e o o e e n n a a b b l l e e i i n n p p u u t t wh ile using mcu interface, it must be connected to v dd . i i n n t t e e r r f f a a c c e e 14 cpu i s s e e l l e e c c t t t t h h e e c c p p u u t t y y p p e e l ow: 80xx-series mcu high: 68xx-series mcu. 15 ps i s s e e l l e e c c t t p p a a r r a a l l l l e e l l / / s s e e r r i i a a l l i i n n t t e e r r f f a a c c e e t t y y p p e e l ow: serial interface high: parallel interface 29 resetb i p p o o w w e e r r r r e e s s e e t t f f o o r r c c o o n n t t r r o o l l l l e e r r a a n n d d d d r r i i v v e e r r this pin is reset signal input. when the pin is low, initialization of the chip is executed. keep this pin pull high during normal operation. 26 csb i c c h h i i p p s s e e l l e e c c t t l ow: seps525 is selected and can be accessed. high: seps525 is not selected and cannot be accessed. 25 rs i d d a a t t a a / / c c o o m m m m a a n n d d c c o o n n t t r r o o l l l ow: command high: parameter/data 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 4 1.5 pin definition (continued) pin number symbol i/o function i i n n t t e e r r f f a a c c e e ( ( c c o o n n t t i i n n u u e e d d ) ) 27 rdb i r r e e a a d d o o r r r r e e a a d d / / w w r r i i t t e e e e n n a a b b l l e e 6 8xx parallel interface: bus enabled strobe(active high) 80xx parallel interface: read strobe signal(active low) while using serial interface, it must be connected to v dd or v ss . 28 wrb i w w r r i i t t e e o o r r r r e e a a d d / / w w r r i i t t e e s s e e l l e e c c t t 6 8xx parallel interface: read (low)/write (high) select 80xx parallel interface: write strobe signal(active low) while using serial interface, it must be connected to v dd or v ss . 16~24 d17~d9 i/o h h o o s s t t d d a a t t a a i i n n p p u u t t / / o o u u t t p p u u t t b b u u s s t hese pins are 9-bit bi-directional data bu s to be connected to the microprocessors data bus. ps description 0 d[17] scl: synchronous clock input d[16] sdi: serial data input d[15] sdo: serial data output 1 9-bit bus: d[17:9] 8-bit bus: d[17:10] while using serial interface, the unused pins must be connected to v ss . r r e e s s e e r r v v e e 1, 35 n.c. (gnd) - r r e e s s e e r r v v e e d d p p i i n n ( ( s s u u p p p p o o r r t t i i n n g g p p i i n n ) ) t he supporting pins can reduce the influences from stresses on the function pins. these pins must be connected to external ground as the esd protection circuit. 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 5 1.6 block diagram s0 vsdh vddh vdd d17 d9 rs csb vsynco vddio vss resetb wrb vssh r2 c5 ~ ~ g1 seps525 g127 ~ ~ ~ ~ osca1 rdb iref c1 c3 osca2 vddh vssh vsdh r1 g0 s479 g126 active area 1.45" 160(rgb) x 128 pixels vsync hsync dotclk enable cpu ps c2 c6 c4 mcu interface selection : base on cpu ps connection and register setting (14h &16h). pins connected to mcu interface : d17~d9, rs, csb, rdb, wrb, and resetb. pins connected to rgb interface : d17~d12, vsync, hsync, dotclk, and enable. eim=1(default) interface mode ps cpu dfm1 dfm0 d17 d16 d15 d14 d13 d12 d11 d10 d9 rs csb rdb wrb resetb 4-wire spi 0 x x x scl sdi nc / i i i i i rs csb ) ) resetb 80xx parallel 9 bit 1 0 1 0 d8 d7 d6 d5 d4 d3 d2 d1 d0 rs csb rdb wrb resetb 80xx parallel 8 bit 1 0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 ) s rs csb rdb wrb resetb 68xx parallel 9 bit 1 1 1 0 d8 d7 d6 d5 d4 d3 d2 d1 d0 rs csb e r/w resetb 68xx parallel 8 bit 1 1 1 1 d7 d6 d5 d4 d3 d2 d1 d0 ) s rs csb e r/w resetb eim=0 interface mode rim1 rim0 d17 d16 d15 d14 d13 d12 d11 d10 d9 vsync hsync dotclk enable 6-bit rgb interface 1 0 d5 d4 d3 d2 d1 d0 ) i i vsync hsync dotclk enable note: 1. dfm1 dfm0 setting by register 16h 2. eim rim1 rim0 setting by register 14h 3. x : dont care, nc : non-connection 1 : connect to vdd or set to high level. 0 : connect to gnd or set to low level. c1 , c3, c5 : 0.1 f c2 : 4.7 f c4, c6 : 4.7 f / 25v tantalum capacitor r1 : 68k r2 : 5.1k 1.69 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 6 2 2 . . a a b b s s o o l l u u t t e e m m a a x x i i m m u u m m r r a a t t i i n n g g s s parameter symbol min max unit notes supply voltage for operation v dd -0.3 4 v 1, 2 supply voltage for i/o pins v ddio -0.3 4 v 1, 2 supply voltage for display v ddh -0.3 16 v 1, 2 operating temperature t op -40 70 c 3 storage temperature t stg -40 85 c 3 life time (75 cd/m 2 ) 10,000 - hour 4 life time (60 cd/m 2 ) 15,000 - hour 4 life time (45 cd/m 2 ) 20,000 - hour 4 note 1: all the above voltages are on the basis of v ss = 0v. note 2: when this module is used beyond the above absolute maximum ratings, permanent breakage of the module may occur. also, for normal operations, it is desirable to use this module under the conditions according to section 3. optics & electrical characteristics. if this module is used beyond these conditions, malfunctioning of the module can occur and the reliability of the module may deteriorate. note 3: the defined temperature ranges do not include the polarizer. the maximum withstood temperature of the polarizer should be 80 c. note 4: v ddh = 14.0v, t a = 25c, 50% checkerboard. software configuration follows section 4.4 initialization. end of lifetime is specified as 50% of initial brightness reached. the average operating lifetime at room temperature is estimated by the accelerated operation at high temperature conditions. 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 7 3 3 . . o o p p t t i i c c s s & & e e l l e e c c t t r r i i c c a a l l c c h h a a r r a a c c t t e e r r i i s s t t i i c c s s 3.1 optics characteristics characteristics symbol conditions min typ max unit brightness l br note 5 60 75 - cd/m 2 c.i.e. (white) (x) (y) c.i.e. 1931 0.26 0.29 0.30 0.33 0.34 0.37 c.i.e. ( red ) (x ) (y) c.i.e. 1931 0.60 0.30 0.64 0.34 0.68 0.38 c.i.e. ( green) (x ) (y) c.i.e. 1931 0.27 0.58 0.31 0.62 0.35 0.66 c.i.e. ( blue ) (x ) (y) c.i.e. 1931 0.10 0.12 0.14 0.16 0.18 0.20 dark room contrast cr - >10,000:1 - viewing angle - free - degree * optical measurement taken at v dd = 2.8v, v ddh = 14.0v. software configuration follows section 4.4 initialization. 3.2 dc characteristics characteristics symbol conditions min typ max unit supply voltage for operation v dd 2.6 2.8 3.3 v supply voltage for i/o pins v ddio 1.6 2.8 v dd v supply voltage for display v ddh note 5 13.5 14.0 14.5 v high level input v ih 0.8 v ddio - v ddio v low level input v il 0 - 0.4 v v oh1 i oh = -0.4ma v high level output v oh2 i oh = -0.4ma v ddio -0.4 - v v ol1 i ol = -0.1ma v low level output v ol2 i ol = -0.1ma - 0.4 v operating current for v dd i dd - 2.5 3.5 ma note 6 - 10.5 13.2 ma note 7 - 14.9 18.6 ma operating current for v ddh i ddh note 8 - 26.2 32.8 ma sleep mode current for v dd i dd, sleep - 3 5 a sleep mode current for v ddh i ddh, sleep - 1 5 a note 5: brightness (l br ) and supply voltage for display (v ddh ) are subject to the change of the panel characteristics and the customers request. note 6: v dd = 2.8v, v ddh = 14.0v, 30% display area turn on. note 7: v dd = 2.8v, v ddh = 14.0v, 50% display area turn on. note 8: v dd = 2.8v, v ddh = 14.0v, 100% display area turn on. * software configuration follows section 4.4 initialization. 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 8 3.3 ac characteristics 3.3.1 68xx-series mpu parallel interface timing characteristics: (v dd = 2.8v, t a = 25c) symbol description min max unit port (read) 10 - ns t ah6 address setup timing (write) 5 - ns (read) 10 - ns t as6 address hold timing (write) 5 - ns csb rs (read) 200 - ns t cyc6 system cycle timing (write) 100 t elr6 read l pulse width 90 - ns t ehr6 read h pulse width 90 - ns t elw6 write l pulse width 45 - ns t ehw6 write h pulse width 45 - ns e t rdd6 read data output delay time 0 70 ns t rdh6 data hold timing * cl = 15pf 0 70 ns t ds6 write data setup timing 40 - ns t dh6 write data hold timing 10 - ns d[17:9] * all the timing reference is 10% and 90% of v ddio . ( read timing ) 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 9 ( write timing ) 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 10 3.3.2 80xx-series mpu parallel interface timing characteristics: (v dd = 2.8v, t a = 25c) symbol description min max unit port t as8 address setup timing 5 - ns t ah8 address hold timing 5 - ns csb rs t cyc8 system cycle timing(read) 200 - ns t rdlr8 read l pulse width 90 - ns t rdhr8 read h pulse width 90 - ns rdb t cyc8 system cycle timing(write) 100 - ns t wrlw8 write l pulse width 45 - ns t wrhw8 write h pulse width 45 - ns wrb t rdd8 read data output delay time - 60 ns t rdh8 data hold timing * cl = 15pf 0 60 ns t ds8 data setup timing 30 - ns t dh8 data hold timing 10 - ns d[17:9] * all the timing reference is 10% and 90% of v ddio . ( read timing ) ( write timing ) 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 11 3.3.3 serial interface timing characteristics: (v dd = 2.8v, t a = 25c) symbol description min max unit port t cycs serial clock cycle 100 - ns t slw scl l pulse width 45 - ns t shw scl h pulse width 45 - ns s cl t dss data setup timing 5 - ns t dhs data hold timing 5 - ns s di t css csb-scl timing 5 - ns t csh csb-hold timing 5 - ns c sb t rss rs-scl timing 5 - ns t rsh rs-hold timing 5 - ns r s * all the timing reference is 10% and 90% of v ddio . 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 12 3.3.4 rgb interface timing characteristics: (v dd = 2.8v, t a = 25c) symbol description min max unit port t dcyc dot clock cycle 100 - ns t dlw dot l pulse width 50 - ns t dhw dot h pulse width 50 - ns dotclk t ds data setup timing 5 - ns t dh data hold timing 5 - ns d[17:12] t vlw vsync pulse width 1 - dotclk t hlw hsync pulse width 1 - dotclk vsync hsync * all the timing reference is 10% and 90% of v ddio . dtst: setup time for data transmission * vsync, hsync, enable, and d[17:12] should be transmitted by 3 clocks for one pixel (rgb). 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 13 4 4 . . f f u u n n c c t t i i o o n n a a l l s s p p e e c c i i f f i i c c a a t t i i o o n n 4.1 commands refer to the technical manual for the seps525 4.2 power down and power up sequence to protect oel panel and extend the panel life time, the driver ic power up/down routine should include a delay period between high voltage and low voltage power sources during turn on/off. it gives the oel panel enough time to complete the action of charge and discharge before/after the operation. 4.2.1 power up sequence: 1. power up v dd & v ddio 2. send display off command 3. initialization 4. clear screen 5. power up v ddh 6. delay 100ms (when v ddh is stable) 7. send display on command 4.2.2 power down sequence: 1. send display off command 2. power down v ddh 3. delay 100ms (when v ddh is reach 0 and panel is completely discharges) 4. power down v dd & v ddio note 9: 1) since an esd protection circuit is connected between v dd , v ddio and v ddh inside the driver ic, v ddh becomes lower than v dd & v ddio whenever v dd & v ddio is on and v ddh is off. 2) v ddh should be kept float (disable) when it is off. 3) power pins (v dd , v ddio , v ddh ) can never be pulled to ground under any circumstance. 4) v dd & v ddio should not be power down before v ddh power down. 4.3 reset circuit when resetb input is low, the chip is initialized with the following status: 1. frame frequency: 90hz 2. oscillation: internal oscillator on 3. ddram write horizontal address: mx1 = 0x00, mx2 = 0x9f 4. ddram write vertical address: my1 = 0x00, my2 = 0x7f 5. display data ram write: hc = 1, vc = 1, hv = 0 6. rgb data swap: off 7. row scan shift direction: g0, g1, , g126, g127 8. column data shift direction: s0, s1, , s478, s479 9. display on/off: off 10. panel display size: fx1 = 0x00, fx2 = 0x9f, fy1 = 0x00, fy1 = 0x7f 11. display data ram read column/row address: fac = 0x00, far = 0x00 12. precharge time (r/g/b): 0 clock 13. precharge current (r/g/b): 0 m a 14. driving current (r/g/b): 0 m a d d i i s s p p l l a a y y o o n n v dd , v dd io v v d d d d , , v v d d d d i i o o o o n n v v d d d d h h o o n n v ss /ground v ddh v v d d d d , , v v d d d d i i o o o o f f f f v dd , v dd io d d i i s s p p l l a a y y o o f f f f v v d d d d h h o o f f f f v ss /ground v ddh 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 14 4.4 actual application example command usage and explanation of an actual example initialized state (parameters as default) powe r up v dd (1ms delay recommended) power up v ddio (1ms delay recommended) set r e s e tb as high (5s delay minimum) set soft_rst 0x05, 0x00 set disp_on_off 0x06, 0x00 set osc_ctl 0x02, 0x01 set display_mode_set 0x13, 0x00 (resetb as low state) set reduce_current 0x04, 0x00 set reduce_current 0x04, 0x01 (1ms delay minimum) v dd /v ddio /v ddh off state (1ms delay minimum) set c lock_div 0x03, 0x30 set duty 0x28, 0x7f set dsl 0x29, 0x00 set memory_accesspointer_x ;8;'e;;; set memory_accesspointer_y 0x21, 0x00 set rgb_if 0x14, 0x31 set rgb_pol 0x15, 0x00 set gray_scale_table 0x50, 0x00 / 0x51, 0x01 / 0x50, 0x01 / 0x51, 0x05 / 0x50, 0x02 / 0x51, 0x09 / 0x50, 0x03 / 0x51, 0x0d / 0x50, 0x04 / 0x51, 0x11 / 0x50, 0x05 / 0x51, 0x15 / 0x50, 0x06 / 0x51, 0x19 / 0x50, 0x07 / 0x51, 0x1d / 0x50, 0x08 / 0x51, 0x21 / 0x50, 0x09 / 0x51, 0x25 / 0x50, 0x0a / 0x51, 0x29 / 0x50, 0x0b / 0x51, 0x2d / 0x50, 0x0c / 0x51, 0x31 / 0x50, 0x0d / 0x51, 0x35 / 0x50, 0x0e / 0x51, 0x39 / 0x50, 0x0f / 0x51, 0x3d / 0x50, 0x10 / 0x51, 0x41 / 0x50, 0x11 / 0x51, 0x45 / 0x50, 0x12 / 0x51, 0x49 / 0x50, 0x13 / 0x51, 0x4d / 0x50, 0x14 / 0x51, 0x51 / 0x50, 0x15 / 0x51, 0x55 / 0x50, 0x16 / 0x51, 0x59 / 0x50, 0x17 / 0x51, 0x5d / 0x50, 0x18 / 0x51, 0x61 / 0x50, 0x19 / 0x51, 0x65 / 0x50, 0x1a / 0x51, 0x69 / 0x50, 0x1b / 0x51, 0x6d / 0x50, 0x1c / 0x51, 0x71 / 0x50, 0x1d / 0x51, 0x75 / 0x50, 0x1e / 0x51, 0x79 / 0x50, 0x1f / 0x51, 0x7d / 0x50, 0x20 / 0x51, 0x01 / 0x50, 0x21 / 0x51, 0x05 / 0x50, 0x22 / 0x51, 0x09 / 0x50, 0x23 / 0x51, 0x0d / 0x50, 0x24 / 0x51, 0x11 / 0x50, 0x25 / 0x51, 0x15 / 0x50, 0x26 / 0x51, 0x19 / 0x50, 0x27 / 0x51, 0x1d / 0x50, 0x28 / 0x51, 0x21 / 0x50, 0x29 / 0x51, 0x25 / 0x50, 0x2a / 0x51, 0x29 / 0x50, 0x2b / 0x51, 0x2d / 0x50, 0x2c / 0x51, 0x31 / 0x50, 0x2d / 0x51, 0x35 / 0x50, 0x2e / 0x51, 0x39 / 0x50, 0x2f / 0x51, 0x3d / 0x50, 0x30 / 0x51, 0x41 / 0x50, 0x31 / 0x51, 0x45 / 0x50, 0x32 / 0x51, 0x49 / 0x50, 0x33 / 0x51, 0x4d / 0x50, 0x34 / 0x51, 0x51 / 0x50, 0x35 / 0x51, 0x55 / 0x50, 0x36 / 0x51, 0x59 / 0x50, 0x37 / 0x51, 0x5d / 0x50, 0x38 / 0x51, 0x61 / initial settings configuration set driving_current_r 0x10, 0x45 s et driving_current_g 0x11, 0x34 s et memory_write_mode 0x16, 0x76 set driving_current_b 0x12, 0x23 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 15 if the noise is accidentally occurred at the displaying window during the operation, please reset the display in order to recover the display function. p ower down v ddh (100ms delay recommended) power down v ddio (1ms delay recommended) set reduce_current 0x04, 0x01 normal operation v dd /v ddio /v ddh off state power down v dd (1ms delay minimum) set my2_addr 0x1a, 0x7f power up v ddh & stabilize d (delay recommended) set d isp_on_off 0x06, 0x01 power stabilized (100ms delay recommended) s et precharge_ current _ b 0x0d, 0x57 display data sent set mx2_addr 0x18, 0x9f set my1_addr 0x19, 0x00 set gray_scale_table 0x50, 0x39 / 0x51, 0x65 / 0x50, 0x3a / 0x51, 0x69 / 0x50, 0x3b / 0x51, 0x6d / 0x50, 0x3c / 0x51, 0x71 / 0x50, 0x3d / 0x51, 0x75 / 0x50, 0x3e / 0x51, 0x79 / 0x50, 0x3f / 0x51, 0x7d / 0x50, 0x40 / 0x51, 0x01 / 0x50, 0x41 / 0x51, 0x05 / 0x50, 0x42 / 0x51, 0x09 / 0x50, 0x43 / 0x51, 0x0d / 0x50, 0x44 / 0x51, 0x11 / 0x50, 0x45 / 0x51, 0x15 / 0x50, 0x46 / 0x51, 0x19 / 0x50, 0x47 / 0x51, 0x1d / 0x50, 0x48 / 0x51, 0x21 / 0x50, 0x49 / 0x51, 0x25 / 0x50, 0x4a / 0x51, 0x29 / 0x50, 0x4b / 0x51, 0x2d / 0x50, 0x4c / 0x51, 0x31 / 0x50, 0x4d / 0x51, 0x35 / 0x50, 0x4e / 0x51, 0x39 / 0x50, 0x4f / 0x51, 0x3d / 0x50, 0x50 / 0x51, 0x41 / 0x50, 0x51 / 0x51, 0x45 / 0x50, 0x52 / 0x51, 0x49 / 0x50, 0x53 / 0x51, 0x4d / 0x50, 0x54 / 0x51, 0x51 / 0x50, 0x55 / 0x51, 0x55 / 0x50, 0x56 / 0x51, 0x59 / 0x50, 0x57 / 0x51, 0x5d / 0x50, 0x58 / 0x51, 0x61 / 0x50, 0x59 / 0x51, 0x65 / 0x50, 0x5a / 0x51, 0x69 / 0x50, 0x5b / 0x51, 0x6d / 0x50, 0x5c / 0x51, 0x71 / 0x50, 0x5d / 0x51, 0x75 / 0x50, 0x5e / 0x51, 0x79 / 0x50, 0x5f / 0x51, 0x7d / set iref 0x80, 0x00 clear screen set mx1_addr 0x17, 0x00 s et precharge_time_r 0x08, 0x04 set precharge_time_g 0x09, 0x05 set precharge_time_b 0x0a, 0x05 s et precharge_ current _r 0x0b, 0x9d s et precharge_ current _ g 0x0c, 0x8c 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 16 power down v b ddh dzzzz set reduce_current 0x04, 0x01 sleep mode normal operation (1ms delay minimum) set reduce_current 0x04, 0x01 power up v b ddh (100ms delay recommended) normal operation sleep mode (1ms delay minimum) set d isp_on_off 0x06, 0x01 set reduce_current 0x04, 0x00 set reduce_current 0x04, 0x00 (1ms delay minimum) (1ms delay minimum) power stabilized (100ms delay recommended) 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 17 5 5 . . r r e e l l i i a a b b i i l l i i t t y y 5.1 contents of reliability tests item conditions criteria high temperature operation 70 c, 240 hrs low temperature operation -40 c, 240 hrs high temperature storage 85 c, 240 hrs low temperature storage -40 c, 240 hrs high temperature/humidity operation 60 c, 90% rh, 120 hrs thermal shock -40 c ? 85 c, 24 cycles 60 mins dwell the operational functions work. * the samples used for the above tests do not include polarizer. * no moisture condensation is observed during tests. 5.2 failure check standard after the completion of the described reliability test, the samples were left at room temperature for 2 hrs prior to conducting the failure test at 23 5 c; 55 15% rh. 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 18 6 6 . . o o u u t t g g o o i i n n g g q q u u a a l l i i t t y y c c o o n n t t r r o o l l s s p p e e c c i i f f i i c c a a t t i i o o n n s s 6.1 environment required customers test & measurement are required to be conducted under the following conditions: temperature: 23 5 c humidity: 55 15% rh fluorescent lamp: 30w distance between the panel & lamp: 50cm distance between the panel & eyes of the inspector: 30cm finger glove (or finger cover) must be worn by the inspector. inspection table or jig must be anti-electrostatic. 6.2 sampling plan level ii, normal inspection, single sampling, mil-std-105e 6.3 criteria & acceptable quality level partition aql definition major 0.65 defects in pattern check (display on) minor 1.0 defects in cosmetic check (display off) 6.3.1 cosmetic check (display off) in non-active area check item classification criteria panel general chipping minor x > 6 mm (along with edge) y > 1 mm (perpendicular to edge) x y x y 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 19 6.3.1 cosmetic check (display off) in non-active area (continued) check item classification criteria panel crack minor any crack is not allowable. copper exposed (even pin or film) minor not allowable by naked eye inspection film or trace damage minor terminal lead prober mark acceptable glue or contamination on pin (couldnt be removed by alcohol) minor ink marking on back side of panel (exclude on film) acceptable ignore for any 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 20 6.3.2 cosmetic check (display off) in active area it is recommended to execute in clear room environment (class 10k) if actual in necessary. check item classification criteria any dirt & scratch on polarizers protective film acceptable ignore for not affect the polarizer scratches, fiber, line-shape defect (on polarizer) minor w 0.1 ignore w > 0.1 l 2 n 1 l > 2 n = 0 dirt, black spot, foreign material, (on polarizer) minor 0.1 ignore 0.1 < 0.25 n 1 0.25 < n = 0 dent, bubbles, white spot (any transparent spot on polarizer) minor 0.5 ignore if no influence on display 0.5 < n = 0 fingerprint, flow mark (on polarizer) minor not allowable * protective film should not be tear off when cosmetic check. ** definition of w & l & (unit: mm): = (a + b) / 2 w l b: minor axis a: major axis 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 21 6.3.3 pattern check (display on) in active area check item classification criteria bright line major missed line major pixel short major darker pixel major wrong display major un-uniform (luminance variation within a display) major 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 22 7 7 . . p p a a c c k k a a g g e e s s p p e e c c i i f f i i c c a a t t i i o o n n s s b pcs tray with vacuum packing p rimary box (l450mm x w296mm x h110mm, b wave) x c set module tray (420mm x 285mm) carton box carton box (major / maximum: l464mm x w313mm x h472mm, ab wave) c set primary box l abel vacuum packing bag sponge protective (370mm x 280mm x 20mm) staggered stacking sponge protective x 1 pcs (empty) x a pcs w rapped with adhesive tape x b pcs item quantity module 420 per primary box holding trays (a) 15 per primary box total trays (b) 16 per primary box (including 1 empty tray) primary box (c) 1~4 per carton (4 as major / maximum) 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 23 8 8 . . p p r r e e c c a a u u t t i i o o n n s s w w h h e e n n u u s s i i n n g g t t h h e e s s e e o o e e l l d d i i s s p p l l a a y y m m o o d d u u l l e e s s 8.1 handling precautions 1) since the display panel is being made of glass, do not apply mechanical impacts such us dropping from a high position. 2) if the display panel is broken by some accident and the internal organic substance leaks out, be careful not to inhale nor lick the organic substance. 3) if pressure is applied to the display surface or its neighborhood of the oel display module, the cell structure may be damaged and be careful not to apply pressure to these sections. 4) the polarizer covering the surface of the oel display module is soft and easily scratched. please be careful when handling the oel display module. 5) when the surface of the polarizer of the oel display module has soil, clean the surface. it takes advantage of by using following adhesion tape. * scotch mending tape no. 810 or an equivalent never try to breathe upon the soiled surface nor wipe the surface using cloth containing solvent such as ethyl alcohol, since the surface of the polarizer will become cloudy. also, pay attention that the following liquid and solvent may spoil the polarizer: * water * ketone * aromatic solvents 6) hold oel display module very carefully when placing oel display module into the system housing. do not apply excessive stress or pressure to oel display module. and, do not over bend the film with electrode pattern layouts. these stresses will influence the display performance. also, secure sufficient rigidity for the outer cases. 7) do not apply stress to the driver ic and the surrounding molded sections. 8) do not disassemble nor modify the oel display module. 9) do not apply input signals while the logic power is off. 10) pay sufficient attention to the working environments when handing oel display modules to prevent occurrence of element breakage accidents by static electricity. * be sure to make human body grounding when handling oel display modules. * be sure to ground tools to use or assembly such as soldering irons. * to suppress generation of static electricity, avoid carrying out assembly work under dry environments. * protective film is being applied to the surface of the display panel of the oel display module. be careful since static electricity may be generated when exfoliating the protective film. 11) protection film is being applied to the surface of the display panel and removes the protection film before assembling it. at this time, if the oel display module has been stored for a long period of time, residue adhesive material of the protection film may remain on the surface of the display panel after removed of the film. in such case, remove the residue material by the method introduced in the above section 5). 12) if electric current is applied when the oel display module is being dewed or when it is placed under high humidity environments, the electrodes may be corroded and be careful to avoid the above. 8.2 storage precautions 1) when storing oel display modules, put them in static electricity preventive bags avoiding exposure to direct sun light nor to lights of fluorescent lamps. and, also, avoiding high temperature and high 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 24 humidity environment or low temperature (less than 0 c) environments. (we recommend you to store these modules in the packaged state when they were shipped from wisechip semiconductor inc.) at that time, be careful not to let water drops adhere to the packages or bags nor let dewing occur with them. 2) if electric current is applied when water drops are adhering to the surface of the oel display module, when the oel display module is being dewed or when it is placed under high humidity environments, the electrodes may be corroded and be careful about the above. 8.3 designing precautions 1) the absolute maximum ratings are the ratings which cannot be exceeded for oel display module, and if these values are exceeded, panel damage may be happen. 2) to prevent occurrence of malfunctioning by noise, pay attention to satisfy the v il and v ih specifications and, at the same time, to make the signal line cable as short as possible. 3) we recommend you to install excess current preventive unit (fuses, etc.) to the power circuit (v dd ). (recommend value: 0.5a) 4) pay sufficient attention to avoid occurrence of mutual noise interference with the neighboring devices. 5) as for emi, take necessary measures on the equipment side basically. 6) when fastening the oel display module, fasten the external plastic housing section. 7) if power supply to the oel display module is forcibly shut down by such errors as taking out the main battery while the oel display panel is in operation, we cannot guarantee the quality of this oel display module. 8) the electric potential to be connected to the rear face of the ic chip should be as follows: seps525 * connection (contact) to any other potential than the above may lead to rupture of the ic. 8.4 precautions when disposing of the oel display modules 1) request the qualified companies to handle industrial wastes when disposing of the oel display modules. or, when burning them, be sure to observe the environmental and hygienic laws and regulations. 8.5 other precautions 1) when an oel display module is operated for a long of time with fixed pattern may remain as an after image or slight contrast deviation may occur. nonetheless, if the operation is interrupted and left unused for a while, normal state can be restored. also, there will be no problem in the reliability of the module. 2) to protect oel display modules from performance drops by static electricity rapture, etc., do not touch the following sections whenever possible while handling the oel display modules. * pins and electrodes * pattern layouts such as the fpc 3) with this oel display module, the oel driver is being exposed. generally speaking, semiconductor elements change their characteristics when light is radiated according to the principle of the solar battery. consequently, if this oel driver is exposed to light, malfunctioning may occur. * design the product and installation method so that the oel driver may be shielded from light in actual usage. * design the product and installation method so that the oel driver may be shielded from light during the inspection processes. 4) although this oel display module stores the operation state data by the commands and the indication data, when excessive external noise, etc. enters into the module, the internal status may be changed. it therefore is necessary to take appropriate measures to suppress noise generation or to protect from influences of noise on the system design. 5) we recommend you to construct its software to make periodical refreshment of the operation 4d systems pty ltd www.4dsystems.com.au
w w i i s s e e c c h h i i p p s s e e m m i i c c o o n n d d u u c c t t o o r r i i n n c c . . doc. no: sas1-0i013-a http://www.wisechip.com.tw 25 statuses (re-setting of the commands and re-transference of the display data) to cope with catastrophic noise. w w a a r r r r a a n n t t y y : : t he warranty period shall last twelve (12) months from the date of delivery. buyer shall be completed to assemble all the processes within the effective twelve (12) months. wisechip semiconductor inc. shall be liable for replacing any products which contain defective material or process which do not conform to the product specification, applicable drawings and specifications during the warranty period. all products must be preserved, handled and appearance to permit efficient handling during warranty period. the warranty coverage would be exclusive while the returned goods are out of the terms above. n n o o t t i i c c e e : : no part of this material may be reproduces or duplicated in any form or by any means without the written permission of wisechip semiconductor inc. wisechip semiconductor inc. reserves the right to make changes to this material without notice. wisechip semiconductor inc. does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of foreign exchange and foreign trade law of taiwan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? wisechip semiconductor inc. 2013, all rights reserved. all other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. 4d systems pty ltd www.4dsystems.com.au

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